Field of the Invention
The present invention lies in the integrated technology field. More specifically, the invention relates to an integrated memory having memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines. The invention furthermore relates to a method for testing and repairing an integrated memory of that type.
Manufacturers generally test integrated semiconductor memories for functionality and repair them as far as possible before delivery of the memories. To that end, the semiconductor memories have not only regular memory cells but also redundant memory cells which can replace a certain proportion of the regular memory cells in the case of defects that have been ascertained. In this context, the redundant memory cells are generally combined in the same way as the regular memory cells to form row lines (word line, WL) and column lines (bit line, BL).
A redundancy concept of this type makes it possible to increase the chip yield during production. After chip fabrication, memory defects are determined by targeted testing and recorded in a defect log. Programmable elements, for example a series of so-called laser fuses, are then used to exchange, in address terms, individual defective row lines or column lines for defect-free redundant row or column lines, respectively.
If laser fuses are used as the programmable elements, then defective row or column lines can only be replaced during the tests at the wafer level. The laser fuses are no longer accessible to the programming laser beam once the chip has been incorporated into a housing.
If electrically programmable fuses, so-called e-fuses, are used as programmable elements, redundancy activation is possible even after the chips have been incorporated into a housing. This is utilized primarily when module defects are not discovered until late in the production or test sequence.
After delivery of the modules, defect correction through the exchange of redundant elements no longer takes place. Defects that occur at this stage lead at worst to the failure of the module and to a return to the manufacturer. In order to preclude this risk, the devices are usually subjected to so-called stress tests, the aim of which is to get as far as possible all susceptible devices to fail whilst still in the test phase with the manufacturer, so that the purchaser only acquires already repaired modules with a low failure probability for the future. However, such stress tests are time-consuming and costly. Moreover, they cannot reduce the failure rate of regular modules after delivery.
This forms the starting point for the invention.
It is an object of the invention to provide a integrated memory device and a method of testing and repairing the same, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for an integrated memory with a low failure probability after delivery.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a plurality of memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines;
the plurality of row lines including regular row lines and redundant row lines;
a self-test unit connected to the memory cell block, the self-test unit:
upon a read access to a current row line, checking for a correctness of a memory cell content read in the read access and, upon detecting a defect, generating a defect signal for the current row line;
for each regular row line, detecting defects thus ascertained and performing a comparison comparing the defects with an average defect for all the regular row lines; and
outputting a row repair signal for the current row line when a predetermined repair condition is met in the comparison;
a self-repair unit connected to the self-test unit, the self-repair unit, in response to receiving the row repair signal, replacing the current row line by a redundant row line during an operation of the integrated memory.
In accordance with an added feature of the invention, the plurality of column lines includes regular column lines and redundant column lines;
the self-test unit:
upon a read access to a current row line, checks the correctness of the memory cell contents read and, in an event of a defect, generates a defect signal for the current row line;
in case of an ascertained defect, compares a calculated signature of the memory cell contents with a previously stored signature, for determining the column line in which the defect occurred;
for each regular row line and for each regular column line, detects the defects ascertained and in each case performs a comparison comparing the defects with an average defect for all of the regular row lines and all of the regular column lines; and
when a predetermined repair condition is met during the comparison, outputs a row repair signal for the current row line or a column repair signal for a column line that has been identified as defective; and
the self-repair unit:
in response to a row repair signal, replaces the current row line by a redundant row line during the operation of the integrated memory; and
in response to a column repair signal, replaces the column line that has been identified as defective by a redundant column line.
In an alternative embodiment of the invention, there is provided an integrated memory, comprising:
memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines;
the plurality of row lines including regular row lines and redundant row lines, and the plurality of column lines including regular column lines and redundant column lines;
a self-test unit connected to the memory cell block and configured to:
in an event of a read access to a current row line, check a correctness of the memory cell contents read and, upon detecting a defect, generate a defect signal for the current row line;
in case of an ascertained defect, compare a calculated signature of the memory cell contents with a previously stored signature, for determining a respective column line in which the defect occurred;
store the complete addresses of the memory cells in which a defect occurred successively in a shift register;
if an address of a same memory cell is repeatedly stored in the shift register, determine the row line and column line associated with the memory cell; and
when a predetermined repair condition is met, output a row repair signal for the associated row line or a column repair signal for the associated column line;
a self-repair unit connected to the self-test unit and configured to:
in response to a row repair signal, replace the current row line by a redundant row line during an operation of the integrated memory; and
in response to a column repair signal, replace the column line that has been identified as defective by a redundant column line.
With the above and other objects in view there is also provided, in accordance with the invention, a method of testing and repairing an integrated memory having memory cells arranged in a memory cell block with a plurality of column lines and a plurality of row lines, and wherein the plurality of row lines includes regular row lines and redundant row lines, the method which comprises the following steps:
reading memory cell contents of a current row line;
checking a correctness of the memory cell contents read;
generating a defect signal for the current row line in a defect case;
detecting the defects ascertained for each regular row line;
comparing a number of defects of the current row line with an average defect for all the regular row lines;
outputting a row repair signal for the current row line when a predetermined repair condition is met in the comparing step; and
replacing the current row line by a redundant row line in response to a row repair signal during an operation of the integrated memory.
In a further alternative of the inventionxe2x80x94applicable when the plurality of row lines includes regular row lines and redundant row lines and the plurality of column lines includes regular column lines and redundant column linesxe2x80x94the method comprises the following steps:
reading memory cell contents of a current row line;
checking a correctness of the memory cell contents read;
in a defect case, comparing a calculated signature of the memory cell contents with a previously stored signature for determining the column line in which the defect occurred;
in a defect case, generating a defect signal for the current row line and a column line determined as defective;
detecting the defects ascertained for each regular row line and each regular column line;
comparing a number of defects of the current row line with an average defect for the regular row lines, and comparing a number of defects of a column line determined as defective with an average defect for the regular column lines;
outputting a row repair signal for the current row line or a column repair signal for a column line identified as defective when a predetermined repair condition is met during the comparing steps; and
replacing the current row line by a redundant row line in response to a row repair signal during an operation of the integrated memory, or replacing the column line identified as defective by a redundant column line in response to a column repair signal.
Finally, there is provided a further method of testing and repairing an integrated memory having memory cells arranged in a memory cell block with a plurality of column lines and a plurality of row lines, the plurality of row lines including regular row lines and redundant row lines and the plurality of column lines including regular column lines and redundant column lines. The method comprises the following steps:
reading memory cell contents of a current row line;
checking a correctness of the memory cell contents;
in a defect case, comparing a calculated signature of the memory cell contents with a previously stored signature for determining the column line in which the defect occurred;
in the defect case, generating a defect signal for the current row line and a column line determined as defective;
storing the complete addresses of the memory cells in which a defect occurred;
testing for repeated storage of the address of the same memory cell;
upon reaching a predetermined number or frequency, determining the row line and column line associated with the memory cell;
outputting a row repair signal for the associated row line or a column repair signal for the associated column line when a predetermined repair condition is met; and
replacing the current row line by a redundant row line in response to a row repair signal during an operation of the integrated memory, or replacing the column line identified as defective by a redundant column line in response to a column repair signal.
In further summary: The integrated memory according to the invention comprises memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines, the plurality of row lines having regular row lines and redundant row lines.
It furthermore comprises a self-test unit, which, in the event of a read access to a present row line, checks the correctness of the memory cell contents read and, in the event of a defect, generates a defect signal for the present row line, which, for each regular row line, detects the defects ascertained and compares them with an average defect for all of the regular row lines, and which outputs a row repair signal for the present row line when a predetermined repair condition is met during the comparison.
The integrated memory furthermore comprises a self-repair unit interacting with the self-test unit, which self-repair unit, in response to a row repair signal, replaces the present row line by a redundant row line in the course of operation of the integrated memory.
Consequently, the invention is based on the concept of using the redundant memory cells that have remained after the functional tests and the defect correction effected by the manufacturer for defect correction in the course of operation of the module. For this purpose, an interacting self-test unit and a self-repair unit (built-in self-repair, BISR) are provided.
In order to decide whether a row line is defective and must be exchanged, the self-test unit logs the number of defects that have occurred for each of the row lines and also an average defect for all of the row lines. If a row line becomes conspicuous, for example through a significantly increased number of defects compared with the average, a repair signal is generated for this row line. The self-repair unit thereupon exchanges the defective row line for a redundant row line in the course of operation.
This measure enables the redundancy of memory cells that is present on the module to be utilized even after delivery to the customer and the failure probability of the memory module thus to be significantly reduced. On the other hand, it is also possible to reduce the test stringency during the manufacturer""s tests and thereby to save time and costs, since it is no longer necessary for all the defects to be corrected as early as at this stage.
Preferably, the self-repair unit has a rewritable memory for rapidly redirecting the address of the present row line to the address of the redundant row line, and an irreversibly programmable memory for the permanent replacement of the present row line by the redundant row line.
This refinement takes account of the observation that the secure and permanent programming of an irreversibly programmable memory, in particular an e-fuse, requires some time, typically one to one thousand microseconds. In order to be able to maintain normal operation of the memory module during this time, the address of the row line to be repaired is temporarily redirected by means of a rewritable memory until the activation of the irreversibly programmable memory is concluded.
In accordance with a preferred refinement, the self-test unit checks the correctness of the read memory cell contents of the present row line using a comparison of a calculated signature of the memory cell contents with a stored signature of the memory cell contents. It is expedient for a signature of the memory cell contents to be calculated and stored for each write access of a row line. If the row line still has redundant bits available, this signature can be stored in a part of these bits.
In this context, what is taken into consideration as a signature is, for instance, the calculation of a check bit, calculation of a checksum or else the use of more complex test polynomials using ECC (error correction code). Simple signatures merely allow identification of the fact that a defect has occurred, while more complex signatures enable the determination of the defect position and in part also a correction of the defect that has occurred. All these methods, known per se, for calculating a signature from the memory contents are taken into consideration in the context of the present invention.
In accordance with an additional feature of the invention, the plurality of column lines has regular column lines and redundant column lines, in which a self-test unit, in the event of a read access to a present row line, checks the correctness of the memory cell contents read and, in the event of a defect, generates a defect signal for the present row line, in the case of an ascertained defect, compares a calculated signature of the memory cell contents with a previously stored signature, for the purpose of determining the column line in which the defect occurred, for each regular row line and for each regular column line, detects the defects ascertained and in each case compares them with an average defect for all of the regular row lines and all of the regular column lines, and when a predetermined repair condition is met during the comparison, outputs a row repair signal for the present row line or a column repair signal for a column line that has been identified as defective.
The self-repair unit of the integrated memory in response to a row repair signal, replaces the present row line by a redundant row line in the course of operation and in response to a column repair signal, replaces the column line that has been identified as defective by a redundant column line. This integrated memory enables not only the above-described repair of row lines but also the repair of defective column lines.
Preferably, the self-repair unit has an irreversible programmable memory for the permanent replacement of the column line that has been identified as defective by the redundant column line, and means for re-establishing the memory cell contents stored in the defective column line. In this case, the re-establishment means can access all of the row lines in order, re-establish the content of the memory cell of the defective column line using an error detection code and store it in the corresponding memory cell of the new, redundant column line.
In accordance with a concomitant feature of the invention, provided as an alternative or in addition to the previously described self-test unit, it is possible to provide a further self-test unit which, in the event of a read access to a present row line checks the correctness of the memory cell contents read and, in the event of a defect, generates a defect signal for the present row line, which, in the case of an ascertained defect, compares a calculated signature of the memory cell contents with a previously stored signature, for the purpose of determining the column line in which the defect occurred, which stores the complete addresses of the memory cells in which a defect occurred successively in a shift register, which, in the case of the address of the same memory cell being repeatedly stored in the shift register, determines the row line and column line associated with the memory cell, and which, when a predetermined repair condition is met, outputs a row repair signal for the associated row line or a column repair signal for the associated column line.
This self-test unit takes account of the fact that many memory cells do not produce a defect in the event of every access (hard defect), but rather fail only occasionally. In order that these memory cells can also be ascertained and replaced, the complete address of a memory cell in which a defect occurred is stored in a shift register. If the same address is stored there repeatedly, the associated memory cell is identified as defective and either the associated row line or the associated column line is replaced by a defect-free redundant line.
Further advantageous refinements, features and details of the inventions emerge from the dependent claims, the following description of the exemplary embodiments, and from the drawing.
Although the invention is illustrated and described herein as embodied in an integrated memory and a method for testing and repairing it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.